Abstract
The authors explore translinear circuits in subthreshold MOS technology and current-mode design techniques for the implementation of neuromorphic analog network processing. The architecture, also known as the Herault-Jutten network, performs an independent component analysis and is essentially a continuous-time recursive linear adaptive filter. Analog I/O interface, weight coefficients, and adaptation blocks are all integrated on the chip. A small network with six neurons and 30 synapses was fabricated in a 2- mu m double-polysilicon, double-metal n-well CMOS process. Circuit designs at the transistor level yield area-efficient implementations for neurons, synapses, and the adaptation blocks. The authors discuss the design methodology and constraints as well as test results from the fabricated chips.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Keywords
Subthreshold conductionNeuromorphic engineeringVery-large-scale integrationComputer scienceChipCMOSArtificial neural networkFilter (signal processing)Electronic engineeringElectronic circuitTransistorEngineeringElectrical engineeringEmbedded systemArtificial intelligenceVoltageTelecommunications
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Publication Info
- Year
- 1992
- Type
- article
- Volume
- 27
- Issue
- 5
- Pages
- 714-727
- Citations
- 58
- Access
- Closed
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Cite This
M.H. Cohen,
Andreas G. Andreou
(1992).
Current-mode subthreshold MOS implementation of the Herault-Jutten autoadaptive network.
IEEE Journal of Solid-State Circuits
, 27
(5)
, 714-727.
https://doi.org/10.1109/4.133158
Identifiers
- DOI
- 10.1109/4.133158