Abstract
The authors formalize the safety analysis of timing properties in real-time systems. The analysis is based on a formal logic, RTL (real-time logic), which is especially suitable for reasoning about the timing behavior of systems. Given the formal specification of a system and a safety assertion to be analyzed, the goal is to relate the safety assertion to the systems specification. There are three distinct cases: (1) the safety assertion is a theorem derivable from the systems specification; (2) the safety assertion is unsatisfiable with respect to the systems specification; or (3) the negation of the safety assertion is satisfiable under certain conditions. A systematic method for performing safety analysis is presented.
Keywords
AssertionComputer scienceNegationProgramming languageFormal specificationFormal verificationSystem requirements specificationFormal methodsTemporal logicSpecification languageSoftware engineering
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Publication Info
- Year
- 1986
- Type
- article
- Volume
- SE-12
- Issue
- 9
- Pages
- 890-904
- Citations
- 631
- Access
- Closed
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Cite This
Farnam Jahanian,
Aloysius K. Mok
(1986).
Safety analysis of timing properties in real-time systems.
IEEE Transactions on Software Engineering
, SE-12
(9)
, 890-904.
https://doi.org/10.1109/tse.1986.6313045
Identifiers
- DOI
- 10.1109/tse.1986.6313045